CS2202 DIGITAL PRINCIPLES AND SYSTEMS DESIGN NOVEMBER/DECEMBER 2009 ANNA UNIVERSITY QUESTION PAPER QUESTION BANK IMPORTANT QUESTIONS 2 MARKS AND 16 MARKS

CS2202 DIGITAL PRINCIPLES AND SYSTEMS DESIGN NOVEMBER/DECEMBER 2009  ANNA UNIVERSITY QUESTION PAPER QUESTION BANK IMPORTANT QUESTIONS 2 MARKS AND 16 MARKS

CS2202 DIGITAL PRINCIPLES AND SYSTEMS DESIGN NOVEMBER/DECEMBER 2009  ANNA UNIVERSITY QUESTION PAPER QUESTION BANK IMPORTANT QUESTIONS 2 MARKS AND 16 MARKS

B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2009

Third Semester

Computer Science and Engineering

CS 2202 — DIGITAL PRINCIPLES AND SYSTEMS DESIGN

(Common to Information Technology)

(Regulation 2008)

Time : Three hours Maximum : 100 Marks

Answer ALL Questions

PART A — (10 × 2 = 20 Marks)

1. Draw the logic diagram for the Boolean expression D ) C B) ((A ′ + using
NAND gates.
2. Perform subtraction using 1’s complement (11010)2 – (10000)2.
3. Perform 9’s and 10’s compliment subtraction between 18 and –24.
4. Draw the logic diagram for half adder.
5. What is the difference between decoder and demultiplexer?
6. What is programmable logic array? How does it differ from ROM?
7. Write down the difference between sequential and combinational circuits.
8. What is race around condition?
9. What is meant by lockout condition?
10. What are the steps for design of asynchronous sequential circuit?

PART B — (5 × 16 = 80 Marks)

11. (a) Simplify the following Boolean expression using Quine McCluskey
method :
∑ + = ) 31 , 11 , 8 ( ) 30 , 29 , 24 , 15 , 9 , 0 ( d m F . (16)
Or
(b) (i) Implement Boolean expression for EXOR gate using NAND and
NOR gates. (8)
(ii) Prove that D ABC E D C D C D C AB + = + + ′ + ′ + + ) )( )( ( . (4)
(iii) Using 2’s complement perform (42)10
– (68)10. (4)
12. (a) (i) Explain the gray code to binary converter with the necessary
diagram. (10)
(ii) Design a half subtractor circuit. (6)
Or
(b) With neat diagram explain BCD subtractor using 9’s and 10’s
complement method. (16)
13. (a) Explain with necessary diagram a BCD to 7 segment display decoder.
(16)
Or
(b) (i) Write the comparison between PROM, PLA, PAL. (6)
(ii) Design a BCD to excess-3 code converter and implement using
PLA. (10)
14. (a) Design and implement a Mod-5 synchronous counter using JK flip-flop.
Draw the timing diagram also. (16)
Or
(b) (i) Explain the working of master slave JK flip-flop. (10)
(ii) Draw the diagram for a 3 bit ripple counter. (6)

15. (a) (i) Design a comparator. (6)
(ii) Design a non sequential ripple counter which will go through the
states 3, 4, 5, 7, 8, 9, 10, 3, 4 .................. draw bush diagram also.
(10)
Or
(b) (i) Design a parity checker. (6)
(ii) Design a sequential circuit with JK flip-flop. (10)